1. Field of the Invention
The invention relates to a method of forming an electrically conductive wiring pattern, and more particularly to a method of forming an electrically conductive wiring pattern on a substrate on which electronic devices such as semiconductor devices are to be mounted.
2. Description of the Related Art
As a conventional method of forming an electrically conductive wiring pattern on a substrate on which semiconductor devices are to be mounted, there are known (a) the subtractive process including the steps of adhering a copper foil onto a substrate, forming a resist pattern on the copper foil, and etching the copper foil by using the resist as a mask, (b) a dry process such as sputtering and evaporation, and (c) the semi-additive process including the steps of forming an underlying metal film on a substrate by a wet process such as electroless deposition, forming a resist pattern on the metal film, precipitating the metal in selected regions by electrolytic plating, and etching the underlying metal film.
However, an electrically conductive wiring pattern formed by whichever process projects beyond a substrate. Hence, when an insulating layer was formed on the wiring pattern and another electrically conductive wiring pattern was further formed on the insulating layer to thereby form a multi-layered wiring structure, it was difficult to form the insulating layer thin and form the multi-layered wiring structure having a planarized surface without a step for ensuring reliable insulating between the upper and lower wiring patterns.
In order to solve this problem, there has been suggested the additive process having the steps of forming a resist pattern directly on a substrate, and precipitating metal in selected regions by electroless deposition to thereby form an electrically conductive wiring pattern. The additive process makes it relatively easy for the electrically conductive wiring pattern to have the same thickness as that of a resist pattern, and hence provides a product having a planarized surface without steps which would be caused by wiring patterns. In addition, the additive process makes it possible to form an insulating layer thinner.
However, since the resist is patterned after a catalyst has been absorbed into a substrate in the above-mentioned processes, the processes are inevitably accompanied with problems that the catalyst is removed in a step of developing the resist, which causes wiring disconnection because of no precipitation of metal, and reduction in adhesion between the resist and the substrate. In addition, since the catalyst is absorbed into the substrate in regions where an electrically conductive wiring pattern is not to be formed, migration of metal ions is likely to take place, which reduces reliability of a final product. These problems become more remarkable in a wiring pattern having a higher density and a smaller width.
There has been also suggested a method wherein catalytic treatment is carried out after the formation of a resist pattern. However, a catalyst is absorbed into a surface of the resist pattern in this method. Accordingly, a metal film is deposited onto a substrate by electroless deposition, there is caused a problem that a bridge is generated between the resist and a metal film with the result of poor insulation therebetween. Hence, this method is not suitable to the formation of a wiring pattern having a higher density and a smaller width.
As a solution to the above-mentioned problems in the additive process, Japanese Unexamined Patent Publication No. 63-289988 has suggested a method of forming an electrically conductive wiring pattern, which includes the steps of forming a substrate having recesses where an electrically conductive wiring pattern is to be formed, forming a thin metal film entirely over the substrate, mechanically removing the thin metal film formed on the resist so that the thin metal film formed in the recesses is left as it is, and forming another metal film on the thin metal film in the recesses by plating.
The method suggested in Japanese Unexamined Patent Publication No. 63-289988 is explained hereinbelow with reference to FIGS. 1A to 1E. First, as illustrated in FIG. 1A, there is formed a substrate 31 having a plurality of recesses 32 at a surface thereof. Then, as illustrated in FIG. 1B, a catalyst layer 33 is formed entirely over the substrate 31. Then, a thin metal film 35 is formed over the substrate 31 by electroless deposition, as illustrated in FIG. 1C. Then, the thin metal film 35 is mechanically removed except portions formed in the recesses 32. As a result, as illustrated in FIG. 1D, a pattern 36a is formed only in the recesses 32. Then, as illustrated in FIG. 1E, the recesses 32 are filled with another metal by plating to thereby form an electrically conductive wiring pattern 36 in the recesses 32 of the substrate 31.
In the method illustrated in FIGS. 1A to 1E, the unwanted portions of the thin metal film 35 are mechanically removed to thereby form the pattern 36a. Herein, the mechanical removal is carried out by means of abrasive materials such as sandpaper and buffers. Hence, if abrasive powders in those abrasive materials had non-uniform diameters, the pattern 36a which is meant to be left as it is in the recesses 32 might be damaged, resulting in a problem of disconnection of the pattern 36a.
It would be possible to avoid the disconnection of the pattern 36a to some degree by employing abrasive powders having smaller diameters. However, as the smaller diameter abrasive powders could provide smaller abrasive force, some portions of the thin metal film 35 which have to be removed would not be removed, in particular, when a pattern is to be formed in a higher density and a smaller width, resulting in poor insulation which would cause short-circuit problems. This problem would become remarkable in a substrate having a greater area, resulting in considerable reduction in a fabrication yield of a device.
Japanese Unexamined Patent Publication No. 5-263216 has suggested another method of forming a metal pattern on a substrate, including the steps of forming a first SiO.sub.2 layer and a second 2MgO--SiO.sub.2 layer on a substrate, forming a resist pattern on the second layer, etching the first and second layers in selected regions with the resist pattern being used as a mask, to thereby form pattern recesses, removing the resist pattern, depositing a metal layer on a surface of the second layer and the pattern recesses, removing the metal layer deposited on a surface of the second layer so that at least a part of the metal layer in the pattern recesses is left as it is and at least a part of the second layer is exposed, and removing the second layer. According to the Publication, the suggested method provides stable lift-off and a pattern having no deformation.
Japanese Unexamined Patent Publication No. 6-140393 has suggested a method of forming an electrode wiring, including the steps of forming an oxide film on a silicon substrate by thermal oxidation, forming the oxide film with a plurality of recesses, forming a thin aluminum film over the oxide film, heating the silicon substrate with a natural oxide film being avoided to generate on a surface of the thin aluminum film, to thereby melt the aluminum film, and filling the recesses with the molten aluminum to thereby form an aluminum electrode wiring.